DS1682S【PDF 9/14 页】IC TIMEKEEPER ALARM ELAPSE 8SOIC

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Sheet目录1994

Note 1: Typical values are at TA = +25°C, VCC = 4.0V.

Note 2: The elapsed time and event counters are backed by three EEPROM arrays, which are used sequentially, allowing up to 3 x

EE. The configuration register, alarm trip-point register, and user memory use a single array, limiting them to one EE.

Note 3: A decoupling capacitor to supply high instantaneous currents during EEPROM writes is recommended. A typical value is

0.01μF. VCC must be maintained above VCC minimum, including transients, during EEPROM writes.

Note 4: VCC must be at or above 2.5V for tEW after the end of an event to ensure data transfer to the EEPROM.

Note 5: Reading data while the contents of EEPROM are transferred to RAM results in incorrect reads.

Note 6: After this period, the first clock pulse is generated.

Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal)

to bridge the undefined region of the falling edge of SCL.

Note 8: The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal.

Note 9: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ 250ns must be met. This is

automatically the case if the device does not stretch the tLOW. If such a device does stretch tLOW, it must output the next

data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released.

Note 10: CB—Total capacitance of one bus line in pF.

SCL

NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).

SDA

STOP

START

REPEATED

START

tBUF

tHD:STA

tHD:DAT

tSU:DAT

tSU:STO

tHD:STA

tSP

tSU:STA

tHIGH

tLOW

DS1682

Total-Elapsed-Time Recorder

with Alarm

www.maximintegrated.com

Maxim Integrated │ 4

Timing Diagram

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